Superscalar Out-of-Order CPU
A superscalar, out-of-order processor designed and validated on an FPGA.
- Period
- January–April 2025
- Kind
- course
- Stack
- VHDL, Quartus Prime, Python
- Guide
- Prof. Virendra Singh, IIT Bombay
- Led a team of four designing and testing a superscalar, out-of-order CPU in VHDL using Quartus Prime.
- Built a custom Python interface for debugging, which made the implement-test loop dramatically less painful than reading waveforms by hand.
- Optimised the design by removing non-synthesisable constructs, and validated it on a MAX 10 FPGA board.